1. Technical Field
The present invention relates to a method of fabricating a semiconductor integrated circuit device. More particularly, the present invention relates to a method of fabricating a semiconductor integrated circuit device that is simpler and less expensive than conventional methods.
2. Description of the Related Art
Due to the increasing demand for high density semiconductor devices, the design rule of semiconductor devices has been decreasing rapidly, and it has become crucial to form smaller patterns to meet the decreased design rule. However, due to the limited resolution of the stepper and scanner used in the photolithography process, it has been difficult to form small patterns, especially patterns smaller than 100 nm.
Many attempts have been made to manufacture vertical transistors in existing semiconductor fabrication processes to overcome transistor characteristic limitations and increase the number of dies formed in a wafer. To fabricate such a vertical transistor, it is necessary to form a round pillar pattern on the semiconductor substrate. However, it is difficult to make a pillar pattern having small design rules in a single attempt. Consequently, in order to achieve a pillar pattern, a line and space pattern is used in two steps to form the pillar pattern with small design rules. In other words, patterning is performed by creating a line and space in one direction, and the space is filled with an oxidation layer. Then another patterning is performed by creating a line and space pattern in the other direction, and a pillar pattern is formed by removing the oxidation layer.
However, in order to form a pillar pattern using the method explained above, the space is filled by an oxidation layer, and therefore a CMP (Chemical Mechanical Polishing) process, where an oxidation layer is deposited and the top of the oxidation layer is planarized, is required. Also, an etching process and a cleaning process are required to remove the oxidation layer that has been patterned. In order to prevent liftoff of an alignment key during LAL (HF and NH4F) liftoff, an I-Line photo process is performed first, and then liftoff is performed after blocking an area to prevent liftoff of the alignment key.
Thus, the production cost is increased due to the complex fabrication process, the high-cost CMP process, and the additional photo process.
The present invention addresses these and other disadvantages of the conventional art.